Innovative Built-In Screening Methodology: Driving Towards Zero Defects in Automotive Microelectronics

The automotive industry, synonymous with precision, safety, and reliability, continually strives to improve the quality and durability of its components. One critical area of concern is the reliability of microelectronic devices, particularly in environments where failure could have catastrophic consequences. As technology advances, vehicles increasingly rely on electronic components for safety, performance, and efficiency. This has necessitated a relentless pursuit of zero defects in automotive microelectronics. This pursuit is driven by stringent quality standards, such as those set by ISO/TS 16949 and IATF 16949, which require manufacturers to adopt robust methodologies to ensure component reliability.

In this context, traditional defect screening methodologies, while effective to some extent, present limitations in cost, time, and scalability. The paper “A New Built-In Screening Methodology to Achieve Zero Defects in the Automotive Environment” by Vezio Malandruccolo et al. introduces an innovative approach to addressing these challenges. This methodology incorporates built-in reliability testing for detecting gate oxide and crystal defects, aiming to enhance defect detection while reducing the need for extensive external testing equipment.

Gate oxide and crystal defects are significant factors in the reliability of microelectronic devices used in automotive applications. These defects can lead to early failures, compromising the safety and functionality of vehicles. The gate oxide, a thin insulating layer in MOS transistors, is susceptible to defects such as pinholes, which can cause breakdowns at lower electric field strengths. These are categorized as Class A defects. Class B defects are extrinsic oxides that fail below the intrinsic breakdown voltage, while Class C defects fail due to intrinsic breakdown above a certain electric field threshold.

Crystal defects, including dislocations and stacking faults, are either inherent in the bulk silicon or induced during manufacturing processes like epitaxial growth and ion implantation. These defects can act as gettering sites for dopant atoms and contaminants, creating highly conductive paths that degrade device performance over time. As these defects accumulate or coalesce, they can lead to device failures, making their detection and mitigation critical in achieving zero defects.

2. Drain Leakage Test (DLT)

The Drain Leakage Test is used to screen for crystal defects by measuring leakage current at the drain terminal of a transistor under stress. Similar to GST, this method applies a high voltage pulse, followed by measuring leakage current to detect the presence of defects. The traditional DLT approach also faces challenges:

• Efficiency of Stress Application: Voltage pulses may not consistently produce permanent damage, leading to inconsistent test results.
• Need for Direct Access: The requirement for direct access to drain contacts limits the application of DLT, especially in modern designs where large power transistors are used internally.
• Burn-In Requirements: DLT often needs to be conducted under burn-in conditions, where devices are stressed at elevated temperatures, increasing the complexity and cost of the screening process.

To address the limitations of traditional GST and DLT methodologies, the paper proposes a novel built-in screening approach that integrates all necessary testing functionalities into the device itself. This built-in testing approach allows each chip to conduct its stress tests autonomously, thus enhancing the screening process’s efficiency and scalability.

1. Working Principle of the Built-In GST and DLT

The built-in screening methodology operates by integrating embedded circuitry capable of generating high voltage stress and monitoring leakage currents directly on the chip. This approach uses the device’s own power supply (e.g., the battery pin VS) to apply the necessary voltage stress, eliminating the need for additional test pads or ATE connections. Key components include:

• High Voltage Generation: A built-in high voltage generator applies the stress to gate oxides or drain terminals.
• Leakage Current Monitoring: Embedded circuitry measures the leakage current, comparing it against predefined thresholds to identify defective devices.
• Digital Control Logic: Internal logic controls the timing and application of stress, ensuring precise testing conditions.

2. Advantages of Built-In GST and DLT

The built-in approach offers several advantages over traditional methods:

• Cost Reduction: By eliminating the need for external ATE and test pads, the built-in method reduces both equipment and testing costs.
• Increased Parallelization: Testing can be conducted simultaneously on a large number of devices, significantly increasing throughput and efficiency.
• Post-Packaging Testing: Built-in GST and DLT can be applied to packaged devices, enabling defect detection at later stages of production and reducing the need for burn-in.
• Minimized Pre-Damage: The reduced handling and direct integration of testing capabilities minimize the risk of introducing defects during the screening process.

The implementation of built-in GST and DLT involves specific design considerations to handle high voltages and accurately measure leakage currents without introducing significant voltage drops. The proposed circuit design includes several key sections:

3. DLT Section

The DLT section mirrors the functionality of the GST section but is designed for stress application at the drain terminal. It includes isolation mechanisms to ensure that stress is only applied during testing, with no impact on normal device operation.

4. Current Monitoring

Accurate measurement of leakage current is critical for defect detection. The built-in circuit includes current mirrors and comparators to monitor leakage current against predefined thresholds. These components are designed to provide high accuracy while operating within the voltage constraints of the device.

The proposed built-in screening circuit was implemented in a layout that occupies approximately 10% of the area of a single LDMOS transistor. SPICE simulations were conducted to validate the design, demonstrating the effective operation of the built-in GST and DLT under various stress conditions. Key findings from the simulations include:

• The built-in circuits successfully applied high voltage stress to gate and drain terminals, with controlled rise and fall times to prevent damage.
• Leakage currents were accurately measured, with thresholds set to detect defect levels typical in automotive applications.
• The digital control logic effectively managed stress application and leakage monitoring, ensuring reliable defect detection.